Improving the Cell Characteristics Using SiN Liner at Active Edge in 4 Gbits NAND Flash Memories

We introduced the self aligned floating poly (SAP) process using the SiN liner at active edge to improve the cell characteristics of high density NAND flash memory devices. Capacitance and electric field at corner of active edge are related to on cell current and cell Vth distributions. In a 70 nm design rule NAND flash cell, we can improve the about 0.2 µA of worst on cell current and cell Vth distributions of 0.5 V respectively. Furthermore, we acknowledged that off cell current of SiN liner is lower than that of oxide liner.