FPGA-based time and cost effective Hamming weight comparators for binary vectors

The paper shows that resources and performance of Hamming weight comparators for binary vectors significantly depend on available basic elements from which the comparators are built and, thus, to optimize the final circuits different design techniques need to be applied. The presented analysis of existing solutions clearly demonstrates that although they may be efficient for one platform (such as fully customized circuits), for another platform (such as FPGA) they become not advantageous at all. The paper suggests several, supplementing each other, Hamming weight counters and comparators based on optimized mapping of the circuits to FPGA look-up tables giving the best performance and the fewest resources compared to the best known alternatives. It is shown that the proposed methods are easily adjustable to a wide range of problem dimensions. Besides, the paper gives well-defined recommendations that enable the most appropriate circuit to be chosen for particular requirements such as the size of the vectors and the required performance. Final evaluations of the results have been done through prototyping in FPGAs and comparison with the best known alternatives.