Hardware Based Steganalysis

Steganalysis is the reverse process of steganography. The goal of steganalysis is to detect, as reliably as possible, the presence of hidden data. Softwarebased steganolytic systems often fail to keep up with high-speed network throughputs. In this chapter, we present the design of a system that automatically detects steg-information in real-time. In this system, RS steganalytic algorithm is parallel implemented with a three-stage pipeline based on FPGA. Experiment results show that this system can achieve very high throughputs (2.5Gbps) and deal with a far larger amount of traffic than software-based approaches.