Soft Errors Induced By Neutrons and Alpha Particles in System on Chips

This Manuscript presents a new low-cost test setup for the radiation tests of System on Chips composed of different functional modules of different nature. Particular attention is given to radiation experiments results of embedded SRAM cores, embedded logic cores and embedded microprocessor cores, highlighting the dissimilar test protocols required to characterize their sensitivity to radiation. The main issues when testing a System on Chip are the cores reduced accessibility and the physical constraints test facilities may impose to the test setup. Manufacturers heavily employ Design for Testability techniques, based on built-in test structures, to enable exhaustive devices testing while minimizing application costs. We reused some of the Design for Testability built-in structures to deeply characterize the cores composing the System on Chip and the overall chip behaviours when exposed to radiation. Our strategy can be applied to any kind of integrated core, and we also present some guidelines on how built-in structures may be fruitfully applied to radiation experiments. Moreover, the monolithic shape of our test board makes it easy to be mounted in most of available particle accelerators chambers or radiation test facilities. As the test structures are built-in and thanks to the efficient interfaces strategy that takes advantage of both JTAG and Wrappers standards, tests are performed at high frequency, thus avoiding Single Event Transients underestimation, but without the need of high-speed connections between a host PC and the DUT, drastically reducing the overall setup costs. This thesis also shows and discusses the results gained during massive radiation experiments campaigns on the available System on Chip manufactured by STMicroelectronics in a 90 nm CMOS technology. As device is meant to be part of a complex automotive design, it may be affected by ground level radiation. We then exposed the chips both to neutron and alpha particles fluxes. With our low-cost setup we measured the SRAM core cross section to alphas and neutrons, and found out that the former one is higher than the latter. We have also characterized the microprocessors behaviour when exposed to alphas. The static test stated that registers flip-flops have a higher radiation induced error rate with respect to code and user RAM one. This result is of great importance, and should be taken into account when building a fault-injection platform. To understand how the corruption of the different memory resources affects codes executions, we designed different benchmark codes and performed a dynamic test. Results demonstrate that, in a typical application, the bit-flips in the code RAM are definitely predominant with respect to the ones in registers. Moreover, we show how code RAM and register bits are not always critical, and their corruption does not necessarily propagate to outputs. Finally, we have considered hardening techniques efficiency and costs. In particular, we have studied how Design For Manufacturing layout modifications and Triple Module Redundancy affect the radiation sensitivity of microprocessors. We considered chips built with different Design For Manufacturing maturity levels, and experimental results demonstrate that an higher level of optimization enhances the resilience to alpha radiation. Hardening techniques, however, come to a cost. The decision on which hardening technique to adopt when building a complex device is a hard-earned trade-off between costs, performance and, of course, reliability. Mitigation strategies for a product then depends on its requirements and on its mission environment.