(Invited) Ultra-Low Power III-V-Based Mosfets and Tunneling FETs

The technical challenges and viable technologies of tunneling MOSFETs (TFET) using III-V semiconductors are present in this paper. Device engineering indispensable in improving the performance of TFETs is summarized. In particular, the electrical characteristics of TFETs using In0.53Ga0.47As/higher-In-content InGaAs/In0.53Ga0.47As quantum well (QW) structures are addressed as viable examples. Also, the effect of surface pre-treatment on InAs on the MOS interface properties, important for the InAs MOSFET and TFET performance, is presented. In addition, the electrical properties of In0.53Ga0.47As MOSFETs using ALD La2O3 gate insulators with ferroelectric-like hysteresis are also introduced as another possible direction for steep slope devices.