The design of low-power fixed-point FIR differentiator IP blocks

This paper presents a method for the generation of low-power Finite duration Impulse Response (FIR) lowpass differentiator Intellectual Property (IP) blocks. The design problem is formulated as a discrete constrained optimization problem where the total squared frequency response approximation error is minimized subject to constraints on the power consumption and frequency response approximation error. It is demonstrated that the power consumption can be reduced while still satisfying the frequency response specifications.