RST Technology for Silicon Ribbons with High Productivity and Low Cost: Present Status and Perspectives

An overview of the development status of the RST (Ribbon on Sacrificial Template) process for the fabrication of low cost crystalline silicon solar cells is presented. Experimental results, correlated with modeling studies, focus on i) the geometrical characteristics of RST ribbons and the wafer production yield, ii) the crystalline texture and the surface morphology of the ribbons, as well as the occurrence of flaws, iii) the electrical properties of mc-Si wafers obtained from the RST process, with an overview of the performances of PV cells made on the wafers, and finally iv) an estimate of the fabrication cost per Wp of RST wafers. Very thin and flat multicrystalline silicon wafers are currently produced over tens of meters at a R&D scale at Solarforce, with high wafer fabrication yield close to 90% and conversion efficiencies above 14%. Based on the present results, the ultimate performances of the process have been estimated and used to evaluate the cost of the RST technology below 18 c€/Wp, with perspectives down to 10 c€/Wp.