Investigation of Novel Si/SiGe Heterostructures and Gate Induced Source Tunneling for Improvement of p-Channel Tunnel Field-Effect Transistors

This paper presents optimization techniques for 20 nm channel length novel Si/SiGe heterojunction p–i–n p-channel tunnel field-effect transistors using extensive device simulations. Three different device architectures are compared. It is shown that depending on the Ge mole fraction in SiGe and the gate voltage, the tunneling could be from the channel to source or within the source only. Due to this, a very careful optimization of the Ge mole fraction is required to achieve optimum performance. It is also shown for the first time that a vertical gate induced source tunneling is present in the devices and that this could be utilized for improving ON state current by increasing the gate–source overlap. Of the three device architectures compared, the structure with SiGe channel and Si source/drain is found to give better ON state current. Gate length scalability is found to be superior for the structure with SiGe source, and Si channel/drain.