Workload-aware Electromigration Analysis in Emerging Spintronic Memory Arrays

Electromigration (EM) has emerged as a major reliability concern for interconnects in advanced technology nodes. Most of the existing EM analysis works focus on the power lines. There exists a limited amount of work which analyzes EM failures in the signal lines. However, various emerging spintronic-based memory technologies such as the Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) and the Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) have high current densities as compared to the conventional Static Random Access Memory (SRAM). These high current densities can lead to EM failures in the signal lines such as bit-line (BL) of these memories. Furthermore, these signal lines have workload-dependent stress as opposed to the conventional DC stress of power distribution networks. In this work, we model the EM failures in the BL of a typical STT memory array with realistic workloads. The analysis is based on physics-based EM model, which is calibrated based on industrial measurement data. The results show that the current densities in the STT arrays can be large enough to cause EM failures in the signal lines with running realistic workloads and that these failures are highly workload-dependent.