Gate-All-Around Strained Si 0.4 Ge 0.6 Nanosheet PMOS on Strain Relaxed Buffer for High Performance Low Power Logic Application

For the first time, we report a short channel high performance, gate-all-around strained Si 0.4 Ge 0.6 nanosheet PMOSFET with aggressively scaled dimensions. We demonstrate realization of s-Si 0.4 Ge 0.6 nanosheet with 5nm thickness and device with L G =25nm featuring record high I ON =508 µA/µm at I OFF =100nA/µm and V DS = -0.5V. This result is obtained with the combination of (a) novel Si-cap-free gate oxide solution featuring thin EOT=9.1A, low D IT and N IT for s-Si 0.4 Ge 0.6 channel, (b) record high hole mobility= 450 cm2/Vs owing to compressive strain imparted by Si 0.7 Ge 0.3 strain relaxed buffer (SRB), (c) low R EXT =150 Ω-µm due to highly active, strained source/drain SiGe process and novel p++ cap layer, (d) optimized source/drain tip and junction to minimize GIDL impact to I OFF . Additionally, the impact of operating temperature on GIDL and I OFF is comprehensively studied to prescribe optimal V CC range of operation for this technology.