Merged 2.5-V and 3.3-V 0.25-μm CMOS technology

ion implants. A dielectric anti-reflective coating (ARC) is deposited over the hard-maskto prevent parasitic reflections and achieve low reflectivity. The dielectric ARC filmconsists of three layers with varying silicon concentration and with different index ofrefraction and extinction coefficient. These layers match the optical properties of theresist to the dielectric ARC. The gate features are finally patterned with deep-UV resistand achieve tight 0.25 im design rules. A distribution of Leff for 10 lots is shown inFig. 2. Hot carrier considerations are quite different for the two supply voltage grades.Hence an extra photolithography is necessary for the NMOS lightly doped drain (LDD)region. Patterned phosphorus LDD implants are used for the 3.3 V NMOS device, whilearsenic implants are used for the 2.5 V NMOS transistor. The 2.5 V and 3.3 V PMOStransistors share the same BF2 LDD implant. TEOS spacers are formed and source-drain(SID)