An integrated 18.75/37.5 GHz FET frequency doubler
1988
The design and performance of an 18.75/37.5-GHz FET frequency doubler is presented. The doubler is implemented in a combination of antipodal finline and suspended microstrip, permitting the entire unit to be integrated on a single substrate. The resulting circuit is a particularly simple and cost-effective component for low- and medium-power applications such as local oscillators. The doubler was built using an NEC673 FET and has a conversion loss of 5.8 dB over a 350-MHz input bandwidth. >
Keywords:
- Correction
- Source
- Cite
- Save
- Machine Reading By IdeaReader
7
References
9
Citations
NaN
KQI