Data Locality on Manycore Architectures

The growing number of cores on modern-day processors and the evolution of their overall architecture continues to bring new challenges to code optimizations for these platforms. Running code on such architectures requires data transfers between the multiple memories located throughout the chip that are expensive in both time and energy. In order to limit the impact of these transfers on the performances of applications we present a new approach that combines both a model for memory-usage and a code transformation. This transformation consists of the rescheduling of code at various levels with the goal of regrouping the different accesses to the same data element in a small window of time. The implementation of this new method is illustrated with multiple use-cases for which the effects on data transfers are evaluated.