Study on Architecture of ATM LSR Supporting VC Merging and Traffic Engineering over It

The explosive growth of the internet traffic in the last few years has imposed tremendous stress on today's routers, particularly in the core network. Recently, ATM LSRs(Label Switching Router) are potentially capable of providing the highest forwarding capacity in the backbone Internet network. VC merging is a mechanism in an ATM LSR that allows many IP routes to be mapped to the same VC label, and provides a scalable mapping method that can support thousands of destinations. VC merging requires reassembly buffers so that cells belonging to different packets intended for the same destination do not interleave with each other. In this study, we propose an architecture of the ATM LSR which supports VC merging. We propose traffic control scheme called APD(Active Packet Discard) algorithm so that predicts and controls the congestion of the Internet traffic effectively. We study the performance of this algorithm using simulation.