DESIGN AND ANALYSIS OF PHASE LOCKED LOOP

The most multipurpose application of the phase locked loops is for clock generation and clock recovery in microprocessor, networking, etc.PLLsis commonly used to generate well-timed on- chip clocks in high performance systems. Modern wireless communication systems employ PLL mainly for synchronization, clock synthesis, skew and jitter reduction. Because of the increase in the speed of the circuit operation, there is a need of the PLL circuit with faster locking ability there is a need of a PLL which must operate in the GHz range with less time. PLL is a mixed signal circuit as its architecture involves both digital and analog signal processing. The present work focuses on the redesign of a PLL system using the 90 nm process technology (GPDK090 library) in the EDA TANNER Design Environment. Here are many circuits has been considered for its superior performance in the form of its low chip area, low power consumption and wide tunable frequency range. The simulation results of the PLL are reported in this work. It is found that the designed PLL consumes less power from a 1.8V DC supply and have a lock time 280.6 ns. As the voltage controlled oscillator (VCO) is the heart of the PLL, so the optimization of the VCO circuit is also carried out using the optimization technique. The results of the VCO designed are shown. KEYWORD: PLL, VCO, GDPK 900, Charge pump (CP).