Development of Glass Interposer with Fine-Pitch Micro Bumps and Warpage Study Depending on Several Glass Substrates with Different CTE's

This paper describes the development of a Glass-Interposer (Glass-IP) with 40um-pitch Cu micro- bumps. It features fine Cu wiring on the front side, Through-hole Glass-Vias (TGV), and a Re-distribution layer (RDL) on back side. After first explaining our process flow, we discuss the warpage of the fully assembled Glass-IP. The focus was on the CTE differences between the Glass-IP and the laminated substrate. The result was the lower CTE of the laminated substrate gave the assembly a lower warpage, while the CTE of Glass-IP had hardly any influence at all. Furthermore, we evaluated two assembly processes for the Glass-IP. One is called “Chip First Process” in which the chips are mounted on Glass-IP first. The other is called “Chip Last Process” where the Glass-IP is mounted on the laminated substrate first. It was confirmed by X-ray observation that the connectivity after full assembly is good for both processes.