Co-optimization of Power, Thermal, and Signal Interconnect for 3D ICs

Historically, advances in the field of packaging and system integration have not progressed at the same rate as ICs. In fact, today’s silicon ancillary technologies have truly become a limiter to the performance gains possible from advances in semiconductor manufacturing, especially due to cooling, power delivery, and ­signaling [1, 2]. Today, it is widely accepted that three-dimensional (3D) system integration is a key enabling technology and has recently gained significant momentum in the semiconductor industry. Three-dimensional integration may be used either to partition a single chip into multiple strata to reduce on-chip global interconnect lengths [3] and/or used to stack chips that are homogeneous or heterogeneous. AQ: Please check if the inserted citation of Fig. 6.1 is appropriate.