A high-speed 2×VDD output buffer with PVT detection using 40-nm CMOS technology

A high-speed compensation technique is proposed to automatically adjust the slew rate of a 2×VDD output buffer. Based on the detected PVT (Process, Voltage, Temperature) corner, the output buffer will turn on different current paths correspondingly to either increase or decrease the output driving current such that the slew rate of the output can be adjusted as well. The proposed design is implemented using a typical 40 nm CMOS process to justify the slew rate compensation performance. By on-silicon measurements, the data rate is 500/460 MHz given 0.9/1.8 V supply voltage with a 20 pF load, the maximum slew rate is 0.53 (V/ns), and the core area of the proposed design is 0.052 × 0.254 mm 2 .