DESIGN AND PROCESS OPTIMIZATION OF THROUGH SILICON VIA INTERPOSER FOR 3D-IC INTEGRATION

The 3D-IC stacking technology provides improved performance, and reduced form factor for applications such as logic-memory integration, image sensors, MEMS, and LED. We present design and fabrication methods to implement Through Silicon Via (TSV) interposer. Cylindrical copper TSV's of 20 μm diameter and 100 μm depth are fabricated in silicon. We present a method for design and process optimization, by recursive enhancement of parameters. Our approach includes selection of materials, proper thicknesses, tolerances, and geometries to achieve the specifications. A discussion on process module optimization and correlation among the whole will be given. We also present an analysis of the relative contribution to cost of each of the modules and identify areas for improvement.