Design and Simulation of a High-Order Sigma-Delta Continuous-Time Modulator

This paper describes the design and simulation of a high order sigma-delta loop filter to use in a feedback loop for the QuADC project. The project target specifications required the selection of a fourth order feedback loop to achieve them. The design includes two loop rates (100 MHz and 20 MHz), and the selected loop was a cascade of integrators with feedforward topology. The simulation results show that the target specification can be achieved by configuring the oversampling ratio and the digital filter according to the measurement bandwidth.