Energy Efficient Reduced Area Overhead Spin-Orbit Torque Non-Volatile SRAMs

This paper proposes two spin orbit torque nonvolatile static random-access memories (SOT-NVSRAMs) with reduced area overhead. One of the proposed cells comprises nine transistors (9T) and a pair of complementary SOT-MTJs and the other comprises seven transistors (7T), two MOM diodes stacked over a pair of complementary SOT-MTJs. The proposed 7T cell has only one overhead transistor compared to the standard 6T SRAM cell, achieving at least 50% reduction compared to other SOT-NVSRAM designs in the literature. Moreover, the always complementary MTJs aid to increase the read margin and speed, leading to at least 20% lower restore energy of our proposed 9T cell compared to others. Furthermore, the two SOT-MTJs are written serially resulting in at least 32% lower store energy of both designs than the counterparts in the literature. In addition, the two SOT-MTJs are totally disconnected from the 6T cell in the nominal SRAM operation, which aids in maintaining the conventional SRAM high performance. Our proposed cell achieves at least 2.2x and 1.9x improvement in a figure-of-merit defined as energy and area product compared to its counterparts in the literature.