Effectiveness of on-die decoupling capacitance in improving chip performance
2008
The paper discusses results of dynamic timing analysis of on-die data and clock synchronization in the presence of power supply noise and shows that chip Fmax performance is less sensitive to amount on-die decoupling capacitance Cdie than it has been conventionally expected. The reason is a positive effect of the clock distribution jitter that neutralizes a negative impact of elevated supply noise after Cdie reduction. The paper shows conditions under which maximum clock frequency Fmax can even increase when Cdie is reduced.
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