High-Speed Multioutput Cla-Adders Using 8-Bit Mcc Adder in Domino Logic

Adders are the critical parts of processor circuits. The performance of processors increases by improving the performance and functionality of adders. Carry look-ahead (CLA) adder’s principle remains dominant in High-speed adder architectures, so the carry delay can be improved by calculating each stage in parallel. In this project by using an 8-bit Manchester carry chain (MCC) adder block in multi output domino CMOS logic. The even and odd carries of this adder are computed in parallel by two independent 4-bit carry chains. Implementation of wider adders based on the use of 8-bit adder module improves the operating speed compared to adders based on the standard 4-bit MCC adder module. Proposed design technique can be used for the implementation of 8, 16, 32 and 64 bit adders in multi output domino logic by using mentor graphics.