PLL USAGE IN THE GENERAL MACHINE TIMING SYSTEM FOR THE LHC

Analogue PLLs have been successfully used for decades to recover clocks and clean the jitter introduced by transmission media. Nevertheless the design parameters are hard to change once the PCB has been mounted. Digital PLLs overcome this problem. They can be either completely digital, substituting the VCO by a Numeric Oscillator, or they can keep a VCXO in case a low jitter is needed. This paper describes both configurations and gives lab results for the latter. This architecture will be used in every General Machine Timing receiver card for the LHC.