Basic PCB Level Assembly Process Methodology for 3D Package-on-Package

The motivation for developing higher density IC packaging continues to be the market and the consumers’ expectation that each new generation of products furnish greater functionality. The miniature IC package evolution began with the development of chip-scale and die-size package technology. These miniature IC package innovations proved ideal for portable and hand-held electronic applications. To address the need for even more functionality without increasing their products size, a number of companies have adapted various forms of multiple-die 3D packaging. A majority of these early multiple function devices relied on the sequential stacking of die elements onto a single substrate interposer. Because the wire-bonding of multiple tiers of uncased die is rather specialized and the die used may have had relatively poor wafer level yields or were not always available in a pre-tested (KGD) condition, overall manufacturing yield of the stacked-die packaged devices have not always met acceptable levels. A key advantage of the package-on-package process is that each layer of the package can be pre-tested before joining. This capability greatly improves the overall manufacturing yield and the functional reliability of the final package assembly is assured. The information furnished in this paper will focus PoP package standards,, substrate design criteria and assembly methodology for efficient in-line assembly processing of vertically stacked IC package elements.