A Highly Scalable, Modular Test Bench Architecture for Large-Scale DC Power Cycling of SiC MOSFETs: Towards Data Enabled Reliability

Silicon carbide (SiC) power MOSFETs have superior conduction, switching and thermal properties compared to silicon (Si) MOSFETs and IGBTs [1]. However, unlike Si devices, whose reliability is well understood from decades of research and field data, SiC device technology is relatively nascent and has only recently started witnessing wide scale deployment. This reliability challenge can possibly be addressed through two complementary solutions as shown in Figure 1: 1) developing a large accelerated aging dataset of SiC devices under various conditions to understand their long term reliability and guide future device development, 2) using on-board, in-system prognostics and device health monitoring techniques to predict imminent device failures well ahead of time, thus ensuring reliable system operation [2]. In both cases, the large-scale reliability testing of SiC MOSFETs is needed. Generally, remaining useful lifetime (RUL) estimation methods for power devices use an empirical model obtained from fitting accelerated aging data [3]-[7], [9], [10]. Consequently, the accuracy of RUL models is directly related to the size and variety of available accelerated aging dataset. Moreover, large datasets are crucial in enabling machine learning (ML) and artificial intelligence (AI) based reliability models.