Chip size semiconductor package using single layer ceramic substrate

1. the art that the invention defined in the claims Chip-size semiconductor package with a single-layer ceramic substrate, 2. The invention attempts to solve the technical challenges To provide a ceramic substrate of a single layer by receiving a semiconductor chip of the LOC method, can frivolous miniaturization than the conventional chip-size package, while intended to provide a chip-sized semiconductor package that can be further improved reliability. 3. Resolution of the subject matter of the invention, Chip, the wire bonding pads formed on the central portion; A ceramic plate having a predetermined size is formed in the rectangular slot having a predetermined size at the center, substrate for installing the chip on the upper surface; Mounting member for mounting the chip on the upper surface of the substrate; It is mounted on the ball mounting portion of the signal circuit to see which is connected to an external circuit; It is filled between the chip and the substrate providing support and protection chip size semiconductor packages made to include a coating to the chip and the substrate. 4. An important use of the invention, And a more compact frivolous possible while improving reliability than conventional packages, there is an effect that is possible to shorten the process in the manufacturing process improves the reduction of the manufacturing cost, workability and productivity