Old Web
English
Sign In
Acemap
>
Paper
>
29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4*64GS/s 8b ADCs and DACs in 20nm CMOS
29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4*64GS/s 8b ADCs and DACs in 20nm CMOS
2017
Cao Jun
Cui Delong
Nazemi Ali
He Tim
Li Guansheng
Catli Burak
Khanpour Mehdi
Hu Kangmin
Ali TAmer
Zhang Heng
Yu Hairong
Rhew Ben
Sheng Shiwei
Shim Yonghyun
Zhang Bo
Momtaz Afshin
Keywords:
Transmitter
Search engine
CMOS
Electrical engineering
Engineering
Flight dynamics (spacecraft)
Correction
Source
Cite
Save
Machine Reading By IdeaReader
0
References
0
Citations
NaN
KQI
[]