Programming the Convey HC-1 with ROCCC 2.0 *

Utilizing FPGAs as hardware accelerators has been hampered by both the availability of affordable platforms and the lack of programming tools that bridge the gap between high-level procedural programming languages and the spatial computing paradigm that is implied on an FPGA. This paper reports on the experiences of programming the Convey Computers HC-1 system, a high-performance hybrid-core system consisting of eight 64-bit Intel Xeon processors coupled with four Xilinx Virtex 5 LX 330 FPGAs, using the ROCCC 2.0 toolset, an open source C to VHDL compilation framework specifically designed for the generation of FPGA-based code accelerators, which address both of these issues. The porting of the ROCCC 2.0 toolset was tested on Dynamic Time Warping, a data mining application, and the ViolaJones face detection algorithm. We discuss the characteristics of these applications and the process of accelerating these applications through ROCCC by writing C that was compiled with ROCCC and mapped onto the HC-1.