DDS with Noise Reduction by Multiplier-Less Filter Methods

Direct Digital Synthesizers have the disadvantage, that they need for a higher spurious free dynamic range (SFDR) a larger bit width to reduce the uniformly distributed white noise caused by the quantization. This leads to large lookup tables, or when methods of noise shaping effects are used, to even larger sizes of the table. So it is necessary to make a trade-off between memory usage and resulting signal quality. This paper focuses on the reduction of the size of the lookup table and reducing the resulting higher noise floor by the combination of multiplierless digital filters, noise shaping and dithering. The advantage of multiplier-less filter implementations are higher clock rates, smaller dial spaces, and on FPGA implementations the usage of DSP blocks is avoided. The latter one is a limiting factor on smaller FPGAs. As final output, this work provides a MATLAB test and design environment followed by a VHDL implementation inclusive testbench.