Fundamental performance differences between CMOS and CCD imagers: Part II
2006
This paper is a status report on recent scientific CMOS imager developments since when previous publications were
written. Focus today is being given on CMOS design and process optimization because fundamental problems affecting
performance are now reasonably well understood. Topics found in this paper include discussions on a low cost custom
scientific CMOS fabrication approach, substrate bias for deep depletion imagers, near IR and x-ray point-spread
performance, custom fabricated high resisitivity epitaxial and SOI silicon wafers for backside illuminated imagers,
buried channel MOSFETs for ultra low noise performance, 1 e- charge transfer imagers, high speed transfer pixels, RTS/
flicker noise versus MOSFET geometry, pixel offset and gain non uniformity measurements, high S/N dCDS/aCDS
signal processors, pixel thermal dark current sources, radiation damage topics, CCDs fabricated in CMOS and future
large CMOS imagers planned at Sarnoff.
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