Scaling of SOI FinFETs down to fin width of 4 nm for the 10nm technology node

Using a novel replacement gate SOI FinFET device structure, we have fabricated FinFETs with fin width (D Fin ) of 4nm, fin pitch (FP) of 40nm, and gate length (L G ) of 20nm. With this structure, we have achieved arrays of thousands of fins for D Fin down to 4nm with robust yield and structural integrity. We observe performance degradation, increased variability, and V T shift as D Fin is reduced. Capacitance measurements agree with quantum confinement behavior which has been predicted to pose a fundamental limit to scaling FinFETs below 10nm L G .