Compact modeling of 3D vertical junctionless gate-all-around silicon nanowire transistors towards 3D logic design

Abstract To sustain transistor scaling beyond lateral 7 nm devices, gate-all-around (GAA) junctionless vertical nanowire field effect transistors (JLNT) are one of the promising alternatives. To overcome the roadblocks of logic cell design using this emerging technology, this work explores compact modeling of 3D GAA-JLNTs based on physics of junctionless transport. The model features an explicit continuous analytical form of drain current calculations adapted for a 14 nm channel junctionless nanowire transistor (JLNT) technology and has been validated against extensive characterization results on a wide range of JLNT geometry, depicting good accuracy. Finally, preliminary simulations have been explored for performance assessment of logic circuits, such as inverters with passive load, active load and complementary topologies as well as ring oscillators, designed using the developed JLNT compact model.