Chip and memory system with data buffer and control method thereof

The invention relates to a semiconductor memory device (400) having a memory cell array (60) and a data buffer (800, 900) for processing data read from the memory cell array (60) or are written in the memory cell array (60), to an integrated circuit device and a storage system and to a related method for controlling the data width. According to the invention a data width control circuit (100, 200, 300) is provided which (ADDR ), the data width of the data buffer (800, 900) in response to an external address signal selectively controls. Using z. As for semiconductor memory devices.