A Novel Test Technique in the SOC Era

In this paper, CBET test approach, a novel test methodology which is a key technology in the SOC era is discussed. CBET test approach adopts both BIST and ATPG and can reduce much test time. It can also alleviates the restriction of external pin count and reduce memory size on LSI tester. A validity of the method is shown theorically and experimentally. CBET is extended to core-based design method which will be a major design method in designing SOC. A test time minimization problem is defined and an efficient algorithm for the problem is given. The method reduces up to 90 % of test time by traditional test method in experiments. And calculation time for our algorithm validates its effectiveness.