A methodology for inserting clock-management strategies in transaction-level models of systemon- chips

Due to the ever-increasing demands on energy efficiency, designers are struggling to construct efficient and correct power management strategies for complex System-on- Chips (SoCs). The validation of an efficient power intent for a SoC is challenging and should be considered at early stage of the electronic system-level (ESL) design flow. To tackle this issue, we propose a high-level modeling approach on top of SystemC/TLM standard allowing the control structure of a power intent to be described in relationship with a functional transaction-level model (TLM) of a SoC. We consider a separation of concern approach in order to make easier the exploration of power intents and the optimization of power consumption. In this paper, the focus is set on an abstract clock intent model through a generic library and a modeling methodology allowing the development of a power management strategy on top of a functional SystemC-TLM model of a virtual prototype. A case study is used to demonstrate by simulation experiments the efficiency of this approach illustrating its capability to analyze effects of power management on performance and power consumption.