On the Impact of Electrical Masking and Timing Analysis on Soft Error Rate Estimation in Deep Submicron Technologies

Soft errors constitute a crucial reliability concern for the Integrated Circuits (ICs) as the continuous CMOS technology downscaling renders them vulnerable to radiation-induced hazards. Therefore, the Soft Error Rate (SER) evaluation represents a necessary process to design radiation-hardened ICs. A SPICE-oriented electrical masking analysis, combined with a TCAD characterization process, contributes to an accurate SER estimation. The impact of a Static Timing Analysis (STA) methodology on SER and the consideration of the actual interconnect delay are discussed. Experimental results on various benchmarks, synthesized with respect to 45nm and 15nm technology, indicate the SER variation as the device scales down.