Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology

In this paper, we study how to boost the performance of FDSOI devices with High-K and Single Metal gate by using the combination of UTBOX GP and local back biasing integrated with our hybrid process. The interest of local back biasing is highlighted in term of V T modulation and power management study on the 45nm 0.374μm 2 bitcells and on the ESD functionality as compared to bulk technology.