Stress Analysis for Chip–Package Interaction of Cu/Low-$k$ Multilayer Interconnects

Delamination failure of a low-k interlayer dielectric (ILD) layer of Cu/low-k multilayer interconnects during a thermal cycle test was investigated by mechanical stress simulation. A three-dimensional (3D) multilevel modeling method was used to analyze the stress that occurred in a fine-scale film stack in a large-scale package. The maximum stress occurred at the low-k/cap film interface that was located at the bottom surface of the low-k ILD layer. This maximum-stress interface coincides with the interface where the delamination occurred. Using this method, the effects of the number of ILD layers, the Young's modulus of the ILD, and the package type on the failure were investigated. This method is useful for reducing delamination failure.