Sense Amplifier Based Comparator Design for SAR ADC

Medical applications, such as biomedical signals compressed sensing, have posed a growing need for low power ADCs with moderate resolution and low sampling frequency. And the SAR ADC could be considered as the suitable choice. The SAR ADC consumes low power due to its simple structure. Moreover, SAR ADC is scalable with the CMOS technology scaling since most parts of the architecture apart from the comparator are digital. Since the comparator, the key building blocks of SAR ADCs, is one of the biggest power consumers, its design must be carefully done in order to optimize the power consumption without a degradation in the performance of the SAR ADC. The design of comparator based on sense amplifier for SAR ADC is provided in this paper. A dynamic latched comparator with PMOSFETS differential inputs is first proposed, which has been verified by the experiments. Then a two-stage dynamic latched comparator with PMOSFETS differential inputs and complementary regenerative output latch is also investigated, which has improved performances.