A Method for Yield and Scaling Characterization of FETs in an InGaP/GaAs Merged HBT-FET (BiFET) Technology

A method for FET yield and scaling analysis of the FET device in a merged FET-HBT GaAs process (BiFET) is described. Using the current-source configuration of a depletion mode FET, a number of devices were connected and stacked together in series and then this stack was replicated into multiple columns; this allows a yield and/or scaling test over a relatively large area. With just one landing of a dc probe, any single device in a 210 device set that has an IDSS that is out of spec will cause a failure that can be quickly identified and its location mapped. In a second type of analysis, a quick measure of device-to-device matching and scaling across a mix of individual and series devices are taken such that any discrepancies can be documented. The matching tests are performed either as side-by-side comparisons or measured over multiple test points as device area is increased progressively. With help from the new structures the root cause of a metal-semiconductor interface problem was quickly identified. It is believed that future BiFET technology iterations will be able to be qualified with fewer development lots and yield targets will be able to be met ahead of schedule.