A 19-GHz PLL with 20.3-fs Jitter

A PLL samples both the rising and falling edges of the reference clock and employs a new retiming method in the feedback divider. Fabricated in 28-nm CMOS technology, the prototype achieves an rms jitter of 20.3 fs from 10 kHz to 100 MHz with a spur of −66 dBc while consuming 12 mW.