A 32-nm Sub-Threshold 9T SRAM Bitcell with Improved Read and Write performance

With the voltage scaling, the stability of data stored in Static Random Access Memory (SRAM) bitcell has become a prime concern. The leakages augmented with noise interference during read and write operation exaggerates the problem further. So, a novel 9T bitcell with improved read and write performance is proposed to address the specified issues. The bitcell provides SNM-free read operation with its unique read assist circuit. It also improves the write performance by incorporating a write assist transistor without much area overhead. The performance of the proposed bitcell is compared with the standard-6T, Dual-V t 7T (DVT-7T) at the low power supply value of 0.4 V by SPICE simulations at 32 nm CMOS technology node. The proposed structure shows significant improvement over other topologies in terms of Read Static Noise Margin (RSNM), Write Static Noise Margin (WSNM), Data Retention Voltage (DRV), critical write time (T crit ), read current (I read ) and standby leakage current (I leak ) values. The proposed-9T structure improves RSNM, WSNM, I read by 169%, 22.6% and 24.3% over standard-6T bitcell respectively. Similarly, performance improvement by 115%, 15%, 207.6%, 97.15%, 81.35% and 50.4% are observed in RSNM, WSNM, I read , T crit (‘0’), T crit (‘1’) and DRV in comparison to the DVT-7T bitcell. A leakage reduction technique to improve the performance has also been suggested in the paper. The impact of process variation on the proposed bitcell is also included.