Silicon Nanowire FET 제작과 DC 및 Low Frequency Noise 특성 분석

In this paper, n-type silicon nanowire FET with a channel width 30 to 500㎚ and length 1 to 5㎛ are fabricated using the mix and match lithography technique. The device shows I ON ~1.25×10?¹, I OFF ~1×10?? (㎃/㎛) and I ON /I OFF ratio of~10? . Extremely low DIBL (2.22㎷/V) indicates the excellent gate controllability of nanowire FET. The average value of extracted volume trap density is about 5.14×10¹?㎝?³eV?¹, which is similar value to each device with different geometry and this result verifies uniformity of our process.