Bridging fault model for single BJT (S-BJT) BiCMOS circuits

Combining the advantages of CMOS and bipolar, BiCMOS is emerging as a major technology for many high performance digital and mixed signal applications. Recent investigations have revealed that bridging faults can be a major failure mode in ICs. This paper presents analysis of bridging faults in S-BJT BiCMOS devices. Effects of bridging faults and a model for computing output voltage levels under bridging with significant resistance is presented. The results obtained with the developed model indicates close relationship with the results obtained by SPICE simulations.