Area-Performance Trade-offs in Tiled Dataflow Architectures

SwansonSteven,PutnamAndrew,MercaldiMartha,MichelsonKen,PetersenAndrew,SchwerinAndrew,OskinMark,J EggersSusan

Area-Performance Trade-offs in Tiled Dataflow Architectures

2006

SwansonSteven
PutnamAndrew
MercaldiMartha
MichelsonKen
PetersenAndrew
SchwerinAndrew
OskinMark
J EggersSusan

Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and performance. The basi...

Keywords:

TRIPS architecture
Application-specific integrated circuit
trade offs
Computer science
Dataflow
Parallel computing
Computer architecture

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