SiGe HBT transistor and layout structure and manufacture method thereof

The invention discloses an SiGe HBT transistor, comprising isolation regions positioned on a silicon substrate, an N-type injection region positioned between the isolation regions, N-type heavily doped regions at two sides of the N-type injection region at the lower sides of the isolation regions, P-type shallow buried layers positioned at the bottoms of the isolation regions and abutted with the N-type injection region and the N-type heavily doped regions, an SiGe region positioned on the isolation regions and the N-type injection region, oxide isolators positioned on the SiGe region, a polycrystalline silicon layer positioned on the oxide isolators and the SiGe region, and side walls positioned at two sides of each of the SiGe region and the polycrystalline silicon layer; the N-type heavily doped regions are led out through deep through holes to form into collectors, and the SiGe region and the polycrystalline silicon layer are led out through contact holes to form into emitters and a base; the area of the polycrystalline silicon layer is smaller than that of the SiGe region. The invention further discloses the layout structure and the manufacture method of the SiGe HBT transistor. According to the SiGe HBT transistor provided by the invention, the breakdown voltage of a device can be improved on the premise of not changing the thickness and the doping concentration of the collector region.