Junction engineering for FDSOI technology speed/power enhancement

This work highlights the way to optimize the speed/power performance of the planar FDSOI technology at the 28nm node and beyond. The combination of gate length shrink and spacerO increase leads to 13% delay decrease and 15% dynamic power saving at same speed through capacitance reduction. It demonstrates that, as far as the access resistance penalty is kept reasonably low, increasing the spacerO is highly efficient to boost AC performance in FDSOI.