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Comparative analysis of BCH-codes decoders implementations with parameters (15, 7, 5) using FPGA
Comparative analysis of BCH-codes decoders implementations with parameters (15, 7, 5) using FPGA
2019
Svetlana E. Ryzhova
Evgeniy Mytsko
Andrey N. Malchukov
Keywords:
Field-programmable gate array
Parallel computing
BCH code
Computer science
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