An integrated system for circuit level hot-carrier evaluation

An integrated system designed to evaluate and predict hot-carrier effects at the circuit level is described. The system will perform device stress, collect data, extract parameters, and simulate circuit aging behavior using the circuit aging simulator from UC Berkeley. Enhancements made to the device-stress and data-analysis portions of the system were found necessary to achieve accurate circuit reliability prediction. Less than 2% error is observed between the measured and simulated performance of a 0.5 mu m ring oscillator test circuit. >